1. Field of the Invention
The present invention relates to a memory control circuit, a semiconductor integrated circuit, and a verification method of a nonvolatile memory.
2. Description of Related Art
In these years, semiconductor integrated circuits have become increasingly sophisticated in function. In accordance with this trend, there is an increasing demand for semiconductor memory devices sophisticated in function. Note that such a semiconductor memory device may be referred to as a “memory” hereinafter. Note that the semiconductor memory is capable of storing data electrically in an erasable or writable manner.
A nonvolatile memory has been widely known as the memory. In this nonvolatile memory, a write processing to write digital data “0” or “1” is performed by injecting charge carriers to floating gates which are provided in each of memory cells. A read processing to read digital data “0” or “1” is performed by detecting an amount of the charge carriers stored in each floating gate of the memory cells. It is arbitrary which data “1” or “0” corresponds to the charge storage state in the floating gate.
In this nonvolatile memory, a readout processing for reading out stored data is first performed, and then a determination processing for determining whether the readout data matches the write data (expectation value data) is performed. By adopting these processings, the reliability of the stored data is secured. If the readout data is different from the write data, a rewrite processing is performed to rewrite the write data to the same memory cells. In other words, if it is determined that a first write processing is failed, the rewrite processing is performed on the same target memory cells. And then, a second determination processing is performed to determine whether the readout data matches the write data as in the first determination processing. Note that it is frequent to perform the write, rewrite, and determination processings per data of a plurality of bits. Note that the determination processing to determine whether the readout data matches the write data may be sometimes referred to a verification processing.
Incidentally, memory cells aligned in a same column or row are coupled to a common wire (a source wire, for example). Therefore, even though the write processing for a particular memory cell is determined to be successful at the determination processing, an opposite result may be obtained sometimes at the subsequent determination processing after the rewrite processing for the particular memory cell.
In Japanese Unexamined Patent Application Publication No. 2000-90675 (reference 1), a determination level at a determination processing is lowered in accordance with the number of times of write processings to a particular memory. More specifically, a level of threshold voltage used in the determination processing is lowered in accordance with the number of times of the write processings to a particular memory.
In the above reference 1, a voltage applied to the memory cells at the first write processing needs to be set with considering a voltage level for a first determination processing in order to perform the first write and determination processings successfully. That is, the voltage applied to the memory cells at the write processing needs to be set high in accordance with a high threshold voltage used in the first determination processing so as to perform the first write and determination processings successfully. If the high voltage is applied to the memory cell, the quality of an insulate film (insulating film formed immediately below the floating gate) of the memory cell may be deteriorated, and thus the reliability of the nonvolatile memory may be deteriorated.
That is, with the prior art, it has been difficult to suppress an overturn of a determination result without deteriorating the reliability of a nonvolatile memory.